Phase locked loop with reduced noise

ABSTRACT

A phase locked loop, comprising: a phase detector configured to determine a phase difference (Δφ) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. §119 of EuropeanPatent application no. 15168348.9, filed on May 20, 2015, the contentsof which are incorporated by reference herein.

FIELD

The present disclosure relates to a phase locked loop with reducedquantization noise.

BACKGROUND

Phase locked loops (or PLLs) are used to generate an output signal witha defined phase relationship to an input reference signal. The outputsignal is matched to the phase of the input reference signal by afeedback loop in which the phase difference between the input referencesignal and the output signal is determined by a phase detector. In adigital phase locked loop, the phase detector outputs a digital signal.The output from the phase detector (indicating phase error) is receivedby a loop filter. The loop filter in turn provides an output signal to afrequency controlled oscillator. In an all-digital phase locked loop,the phase detector may output a digital signal, the loop filter may be adigital loop filter, and the frequency controlled oscillator may be adigitally controlled oscillator.

Phase locked loops are often required to achieve a specific noiseperformance. The maximum allowable phase noise may be determined by anintended application for a phase locked loop.

Sources of phase noise in a phase locked loop may include: externaloscillator noise (resulting from an imperfect reference oscillatorsignal); frequency controlled oscillator noise, and quantization noise,arising from quantization of the phase error at the phase detector.

A phase locked loop with reduced noise is desirable.

SUMMARY

According to a first aspect, there is provided a phase locked loop,comprising:

a phase detector configured to determine a phase difference between areference signal and a feedback signal;

a loop filter configured to perform a filtering operation on a signalderived from the phase difference and to provide a control signal;

a frequency controlled oscillator configured to receive the controlsignal and provide an output signal with a frequency that variesaccording to the control signal;

wherein a low-pass filter is provided between the phase detector and theloop filter and/or between the loop filter and the frequency controlledoscillator, to reduce quantization noise from the phase detector.

The phase locked loop may have a bandwidth defined by thecharacteristics of the phase detector, loop filter and frequencycontrolled oscillator. The low pass filter may have a cut-off frequencythat is greater than the bandwidth. The low pass filter may therebysuppress out-of-band quantization noise, without substantially affectingloop stability and performance.

The low-pass filter may have a cut-off frequency at least 1.2 times thebandwidth. The low-pass filter may have a cut-off frequency of at least:1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2 times the bandwidth.

The low-pass filter may have a cut-off frequency that is at least 100kHz greater than the bandwidth. The low lass filter may have a cut-offfrequency that is at least 50, 200, 300, or 500 kHz greater than thebandwidth.

The low-pass filter may comprise a first order IIR (infinite impulseresponse) filter. The low-pass filter may comprise a second order IIRfilter. The low-pass filter may be a finite impulse response filer. Thelow-pass filter may be a digital filter. A first order digital IIRfilter is simple and effective in some applications.

The low-pass filter may comprise a shift multiplier in a forward paththereof, for multiplying by an integer power of two. A shift multipliermay be a convenient way to provide a multiplication function.

The loop filter may comprise an integral path comprising an integrator.

The loop filter may comprise a proportional path.

The phase locked loop may be configured with: a proportional gain factork_(p) in the proportional path and an integral gain factor k_(i) priorto the integrator in the integral path. Optionally, k_(p)≦2⁻¹²; and/ork_(i)≦2⁻¹⁸.

The frequency controlled oscillator may comprise a switched capacitor LCoscillator. The frequency controlled oscillator may be a digitallycontrolled oscillator. Alternatively, the frequency controlledoscillator may be a voltage controlled oscillator (e.g. having avaractor).

The control signal may be a digital signal.

The output signal from the phase detector may be a digital signal.

The loop filter may be a digital loop filter.

The phase locked loop may be an all-digital phase locked loop.

A transmitter or receiver is provided, comprising the phase locked loopaccording to the first aspect.

The receiver may be a satellite radio receiver.

These and other aspects of the invention will be apparent from, andelucidated with reference to, the embodiments described hereinafter.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments will be described, by way of example only, with reference tothe drawings, in which

FIG. 1 is a block diagram of a phase locked loop;

FIG. 2 is a system block diagram used to calculate the phase transferfunction for a phase locked loop;

FIG. 3 is system block diagram used to calculate phase transfer functionfor a phase locked loop, including oscillator phase noise;

FIG. 4 is a graph showing the high-pass and low-pass characteristics ofthe transfer function of the system in FIG. 3;

FIG. 5 is graph showing phase noise contributions from quantizationnoise and oscillator noise for the transfer function of FIG. 3 for afirst bandwidth;

FIG. 6 is a graph showing phase noise contributions from quantizationnoise and oscillator noise for the transfer function of FIG. 3 for asecond, lower, bandwidth;

FIG. 7 is a used to calculate the phase transfer function for a phaselocked loop according to an embodiment, in which (a) depicts the overallphase locked loop, and (b) depicts an example low pass filter;

FIG. 8 is a graph showing the high-pass and low-pass characteristics ofthe transfer function of FIG. 7;

FIG. 9 is a graph showing phase noise contributions from quantizationnoise and oscillator noise for the transfer function of FIG. 7;

FIG. 10 is a simulation comparing phase noise for: a free running(open-loop) frequency controlled oscillator, a phase locked loopaccording FIG. 2, and a phase locked loop according to an embodiment;and

FIG. 11 is a simulation comparing phase noise for: a free running(open-loop) frequency controlled oscillator and a phase locked loopaccording to an embodiment with different low-pass filterconfigurations.

It should be noted that the figures are diagrammatic and not drawn toscale. Relative dimensions and proportions of parts of these figureshave been shown exaggerated or reduced in size, for the sake of clarityand convenience in the drawings. The same reference signs are generallyused to refer to corresponding or similar feature in modified anddifferent embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 is a block diagram of a (all-) digital phase locked loop,comprising a reference phase generator 110, phase detector 115, loopfilter 120, digitally controlled oscillator (DCO) 130, post divider 140,control block 150, time to digital converter (TDC) 160, frequencydivider 170, feedback register 180 and crystal 190.

The crystal 190 provides an output signal with a stable frequency (e.g.60 MHz), which is used to clock the TDC 160, feedback register 180 andthe register 113 of the reference phase generator 110.

The reference phase generator 110 comprises an adder 111 and register113, arranged to integrate an input frequency control word FCW, andprovide a reference phase ramp φ_(ref).

A phase detector 115 compares the reference phase ramp φ_(ref) with afeedback ramp φ_(fb) derived from the output of the DCO 130, and outputsa phase error signal Δφ. The feedback ramp φ_(fb) is determined bycombining (e.g. by fixed point concatenation) the output from thefeedback register 180 and the TDC 160.

The loop filter 120 receives the phase error signal Δφ, and performs afiltering operation. The loop filter 120 in this example is controlledby a control block 150, which may vary the configuration of the loopfilter 120 (e.g. depending on the set FCW). The loop filter 120 providesthree output signals for controlling the DCO 130, these being a processvoltage temperature control signal PVT, an acquisition control signalACQ, and a tracking signal TR. Each of these control signals may controla switched capacitor bank of the DCO 130, so as to vary the outputfrequency of the DCO 130. Other frequency control mechanisms, such asdigital to analog converters with varactors may be used in alternativearrangements.

The output from the DCO 130 is received at the frequency divider 170 andthe TDC 160. The TDC measures and quantizes the timing differencebetween transitions of the output signal from the crystal 190 and thetransitions in the output from the DCO 130. The frequency divider 170divides the output frequency of the DCO to produce a signal with reducedfrequency. The output from the frequency divider 170 is received at thefeedback register 180, which accumulates a count of the transitions inthe output of the divider

The post divider 140 receives the output from the DCO 130, and dividesthe frequency by a factor, P, so as to provide an output signal from thephase locked loop at an appropriate frequency.

As an illustrative example, the output from the DCO 130 may have afrequency of around 5 GHz. The tuning range of the DCO 130 may be around2.5 MHz. The post divider factor P may be 50, resulting in a phaselocked loop output frequency of 100 MHz and a tuning range of 50 kHz.The PVT capacitor bank of the DCO 130 may have a tuning resolution ofaround 10 MHz, the ACQ capacitor bank may have a tuning resolution ofaround 0.5 to 1 MHz, and the TR capacitor bank may have a tuningresolution on the order of 10 to 50 kHz.

The DCO 130 and crystal 190 may operate in the analog domain. The DCOside of the divider 170 and TDC 160 may also operate in the analogdomain. The remaining components may operate in the digital domain.

FIG. 2 is a system block diagram for calculation of a phase transferfunction for a phase locked loop (similar to that of FIG. 1), comprisinga phase detector 115, differential gain block 116, loop filter 120 andDCO 130. The phase detector 115 receives an input reference phaseφ_(ref) and subtracts the feedback phase φ_(fb) output from the DCO 130.The DCO 130 is represented by the transfer s-function k_(o)/s (i.e. anintegrator block with gain k_(o)). The output of the phase detector 115is multiplied by a differential gain factor k_(d) at the differentialgain block 116. The output of the differential gain block 116 isprovided to the loop filter 120.

The loop filter 120 comprises a proportional path 121 and an integralpath 125. In the proportional path 121, the output of the differentialgain block 116 is multiplied (at proportional gain block 122) by aproportional gain factor k_(p). In the integral path 125, the output ofthe differential gain block 116 is first multiplied by an integral gainfactor k_(i) (at integral gain block 126), and then integrated (atintegrator 127). The output from the proportional and integral paths121, 125 are summed at output summing block 129, to provide the loopfilter output, which is in turn received at the DCO block 130.

This model can be generalised to calculate the phase noise contributionfrom the phase reference φ_(ref) and the noise φ_(n,dco) from the DCO,as shown in FIG. 3.

FIG. 3 shows the same model as FIG. 2, but the loop filter 120 has beenreplaced with a single block, in which LF represents the transferfunction of the loop filter 120, and the DCO noise contributionφ_(n,dco) has been included by way of a noise adding block 195.

The phase transfer function for the diagram of FIG. 3 can be written as:

$\begin{matrix}{\varphi_{out} = {{\varphi_{ref} \cdot \frac{k_{d} \cdot {LF} \cdot k_{o}}{s + {k_{d} \cdot {LF} \cdot k_{o}}}} + {\varphi_{n,{dco}} \cdot \frac{s}{s + {k_{d} \cdot {LF} \cdot k_{o}}}}}} & (1)\end{matrix}$

If the loop filter transfer function is as represented in FIG. 2, thisresults in:

$\begin{matrix}{\varphi_{out} = {{\varphi_{ref} \cdot \frac{{k_{d} \cdot k_{p} \cdot k_{o} \cdot s} + {k_{d} \cdot k_{i} \cdot k_{o}}}{s^{2} + {k_{d} \cdot k_{p} \cdot k_{o} \cdot s} + {k_{d} \cdot k_{i} \cdot k_{o}}}} + {\varphi_{n,{dco}} \cdot \frac{s^{2}}{s^{2} + {k_{d} \cdot k_{p} \cdot k_{o} \cdot s} + {k_{d} \cdot k_{i} \cdot k_{o}}}}}} & (2)\end{matrix}$

This can be written in terms of the classical damping factor and naturalfrequency ω_(n), as:

$\begin{matrix}{\varphi_{out} = {{\varphi_{ref} \cdot \frac{{2 \cdot \xi \cdot \omega_{n} \cdot s} + \omega_{n}^{2}}{s^{2} + {2 \cdot \xi \cdot \omega_{n} \cdot s} + \omega_{n}^{2}}} + {\varphi_{n,{dco}} \cdot \frac{s^{2}}{s^{2} + {2 \cdot \xi \cdot \omega_{n} \cdot s} + \omega_{n}^{2}}}}} & (3)\end{matrix}$with k_(d)·k_(i)·k_(o)=ω_(n) ² and k_(d)·k_(p)·k_(o)=2·ξ·ω_(n).

It is directly visible from equation (3) that the loop has a low pass(LP) characteristic including the reference phase φ_(ref) and a highpass (HP) characteristic including the phase noise from the oscillatorφ_(n,dco). The bandwidth of the loop filter is defined by the cut-offfrequency ω_(3 dB) which depends on the natural frequency, ω_(n) and thedamping factor ξ.

Looking at equation (1), the denominator of the reference phase termφ_(ref) always has one order less than the denominator. Hence the lowpass characteristic has a −20 dB/decade slope, following the cut-offfrequency, ω_(3 dB). The oscillator phase noise term φ_(n,dco), however,depends on the order of the loop filter 120 (as is clear from equation(1)). In the example of equation (3), which is a 2^(nd) order system,the oscillator phase noise contribution has a 40 dB/dec slope before thecut-off frequency, ω_(3 dB).

FIG. 4 depicts the phase noise contributions from the HP term 201 andthe LP term 202 for the 2^(nd) order PLL system of equation (3). In theexample of FIG. 4 the bandwidth, ω_(3 dB), of the PLL is selected sothat the noise contributions from the HP term 201 and the low pass term202 are similar at the cutoff frequency determined by the PLL bandwidth(where each term starts to roll-off).

Referring back to equation (3), the phase noise contribution to the termφ_(ref) from the reference oscillator itself (e.g. crystal 190 inFIG. 1) may be neglected in the frequency range of interest because inthis frequency range the reference noise contribution φ_(ref) isdominated by the quantization noise arising from the resolution of thephase detector 115. This quantization noise is white noise, and isconstant over frequency. Quantisation noise may be represented by thefollowing equation:

$\begin{matrix}{{L_{quant}(f)} = {\frac{1}{12}\left( \frac{\tau_{res}}{T_{dco}} \right)^{2}\frac{1}{2{\pi \cdot f_{ref}}}}} & (4)\end{matrix}$where τ_(res) is the phase detector resolution, T_(dco) the DCO periodand f_(ref) the reference frequency.

The noise contributions from the DCO to the term φ_(n,dco) include afree running phase noise that has a slope of −30 dB/decade in theflicker noise range, and thermal noise which has a slope of −20dB/decade above a certain frequency (e.g. between 10 kHz and 100 kHz).Since it is desirable for a phase locked loop to have a high bandwidth,only thermal noise is of interest in the following analysis.

FIG. 5 shows a graph that includes DCO thermal noise 221, quantizationnoise 222 and the total phase noise 220 of the PLL. The DCO thermalnoise 221 reduces at −20 dB/decade in the out-of band range (i.e. atfrequencies greater than the bandwidth, ω_(3 dB)), which is the samerate of reduction as the quantization noise (which although white noise,is LP filtered). In this example, near the cut-off frequency, ω_(3 dB),the noise contributions from the DCO thermal noise 221 and quantizationnoise 222 are similar. This results in around 3 dB more total phasenoise around ω_(3 dB) than the DCO thermal noise contribution, whichwould be the limiting factor for such a phase locked loop.

For a number of applications (e.g. consumer and automotivecommunications systems) it is very important to have an out-of-bandphase noise that is as low as possible. Small changes of the phase noiselevel can have a high impact on the functioning of a system thatincludes the PLL. An improvement of 1 or 2 dB can have big impact to thecomplete system. In the example of FIG. 5, any improvements of the DCOphase noise would not have a significant impact because the phase noiseis dominated by the quantization noise 222.

A trivial solution to the quantization noise dominating the overallphase noise of a PLL is to reduce the bandwidth ω_(3 dB), so that theout-of-band phase noise is in fact dominated by the DCO thermal noise.FIG. 6 depicts this, showing DCO thermal noise 231, quantization noise231 and total phase noise 230. Decreasing the bandwidth of the PLLreduces the cut-off frequency of the LP term in equation (3), whichallows the phase noise contribution from the DCO to produce anundesirable peak near the cut-off frequency ω_(3 dB). This peak can onlybe avoided if the DCO phase noise is reduced, but this is verychallenging in practice. The DCO design may already be at or near thephysical limits of noise performance. A further disadvantage of reducingbandwidth is an increased locking and settling time of the PLL.

FIG. 7(a) shows a PLL architecture that ameliorates the above mentionedissues. The PLL of FIG. 7 is the same as that of FIG. 2, except that anadditional low pass filter 250 is included between the loop filter 120and frequency controlled oscillator 130. In other embodiments, theadditional low pass filter 250 can be placed between the loop filter 120and the phase detector 115, and still provide the same benefits. Theadditional low pass filter 250 may have a cutoff frequency that is thesame as, or higher than the bandwidth of the phase locked loop.

FIG. 7(b) shows an example architecture for the low pass filter 250,comprising a first order infinite impulse response (IIR) filter. Theforward path of the low pass filter 250 of FIG. 7(b) comprises (inorder) a first summing block 251, multiplier 252, second summing block253 and unit delay 254. The output from the unit delay 254 is fed-backto the first summing block 251, where it is subtracted from the inputsignal to the filter 250, and to the second summing block 253, where itis added to the output of the multiplier 252. The multiplier 252 appliesa gain factor a to the output of the first summing block 253, and passesthe result to the second summing block 253.

The low pass filter 250 of FIG. 7(b) has the following frequencyresponse:

$\begin{matrix}{\frac{out}{in} = {\frac{\frac{a}{z - 1}}{1 + \frac{a}{z - 1}} = {\frac{a}{z - 1 + a}\overset{z = {e^{sT} \approx {1 + {sT}}}}{\rightarrow}\left. \frac{\frac{a}{T}}{s + \frac{a}{T}}\rightarrow\frac{\omega_{c}}{s + \omega_{c}} \right.}}} & (5)\end{matrix}$

The multiplier 252 may be a shift multiplier, and a=2^(−klp) where klpis the low pass filter factor. The cut-off frequency of the low passfilter 250 may then be calculated as:

$\begin{matrix}{\omega_{c} = {{\frac{a}{T}->f_{c}} = {\frac{a}{2{\pi \cdot T}} = \frac{2^{- {klp}}}{2{\pi \cdot T}}}}} & (6)\end{matrix}$

The overall phase transfer function for the phase locked loop of FIG.7(a) may then be written as:

$\begin{matrix}{\varphi_{out} = {{\varphi_{ref} \cdot \frac{{k_{d} \cdot k_{p} \cdot k_{o} \cdot a \cdot {sT}} + {k_{d} \cdot k_{i} \cdot k_{o} \cdot a}}{{s^{3}T^{3}} + {{a \cdot s^{2}}T^{2}} + {k_{d} \cdot k_{p} \cdot k_{o} \cdot a \cdot {sT}} + {k_{d} \cdot k_{i} \cdot k_{o} \cdot a}}} + {\varphi_{n,{dco}} \cdot \frac{{s^{3}T^{3}} + {{a \cdot s^{2}}T^{2}}}{{s^{3}T^{3}} + {{\omega_{c} \cdot s^{2}}T^{2}} + {k_{d} \cdot k_{p} \cdot k_{o} \cdot \omega_{c} \cdot {sT}} + {k_{d} \cdot k_{i} \cdot k_{o} \cdot \omega_{c}}}}}} & (7)\end{matrix}$or, in terms of ξ and ω_(n), as:

$\begin{matrix}{\varphi_{out} = {{{\varphi_{ref} \cdot \frac{{{2 \cdot \xi \cdot \omega_{n}}{\frac{a}{T} \cdot s}} + {\omega_{n}^{2}\frac{a}{T}}}{s^{3} + {\frac{a}{T}s^{2}} + {{2 \cdot \xi \cdot \omega_{n}}{\frac{a}{T} \cdot s}} + {\omega_{n}^{2}\frac{a}{T}}}} + {\varphi_{n,{dco}} \cdot \frac{s^{3} + {\frac{a}{T} \cdot s^{2}}}{s^{3} + {\frac{a}{T}s^{2}} + {{2 \cdot \xi \cdot \omega_{n}}{\frac{a}{T} \cdot s}} + {\omega_{n}^{2}\frac{a}{T}}}}} = {{\varphi_{ref} \cdot \frac{{2 \cdot \xi \cdot \omega_{n} \cdot \omega_{c} \cdot s} + {\omega_{n}^{2} \cdot \omega_{c}}}{s^{3} + {\omega_{c}s^{2}} + {2 \cdot \xi \cdot \omega_{n} \cdot \omega_{c} \cdot s} + {\omega_{n}^{2} \cdot \omega_{c}}}} + {\varphi_{n,{dco}} \cdot \frac{s^{3} + {\omega_{c} \cdot s^{2}}}{s^{3} + {\omega_{c}s^{2}} + {2 \cdot \xi \cdot \omega_{n} \cdot \omega_{c} \cdot s} + {\omega_{n}^{2} \cdot \omega_{c}}}}}}} & (8)\end{matrix}$

In common with equation (3), equation (8) has low pass (LP)characteristic including the reference phase φ_(ref) and a high pass(HP) characteristic including the phase noise from the oscillatorφ_(n,dco).

FIG. 8 depicts the phase noise contributions from the HP term 211 andthe LP term 212 for the PLL system of equation (8).

Since the order of the denominator of the reference phase term φ_(ref)in equation (8) is 3 whereas the numerator is 1, the cut off slope ofthe low pass behaviour is −40 dB/decade. The suppression of thequantization phase noise is therefore stronger than the slope of the DCOthermal phase noise (at −20 dB/decade).

If the order of the additional low pass filter 250 in FIG. 7(b) washigher (for example second order, such as a second order IIR filter),the slope of the high pass characteristic can be increased (for exampleto −60 dB/dec in the case of a 2nd order low pass filter 250).

The high pass characteristic of the overall phase locked loop is notchanged significantly. For low frequencies the 2nd order term dominates,and the high pass characteristic is still 40 dB/dec as before, as shownin FIG. 8.

FIG. 9 shows the total phase noise 240 for a PLL as shown in FIG. 7,along with DCO thermal noise component 241 and the quantization noisecomponent 242. In this example, the cut-off frequency ω_(c) of theadditional low pass filter 250 is 1 MHz, and the PLL bandwidth ω_(3 dB)is 100 kHz.

For higher frequencies the slope of the phase detector quantizationnoise 242 is increased from −20 dB/decade to −40 dB/decade, whichresults in sufficient reduction of quantization noise for the DCO phasenoise 241 to become the dominant source of total phase noise 204.

The performance of a phase locked loop comprising an additional low passfilter has been simulated. A loop filter according to an embodiment(e.g. as shown in FIG. 7) was implemented and the phase noisecontribution modeled, based on measurement results.

FIG. 10 shows simulation results, comparing phase noise 270 from a freerunning (open loop) DCO with phase noise 260 according to thearchitecture of FIG. 2 (without an additional low pass filter) and phasenoise 273 from the architecture of FIG. 7, including the low pass filter250. For both closed loop phase noise simulations 260, 253, k_(p)=2⁻¹²and k_(i)=2⁻¹⁹. The reference frequency for these simulations is 55.5MHz. For the phase noise simulation 273 including the low pass filter,klp=3, corresponding with a cut-off frequency ω_(c) for the low passfilter 250 of approximately 1.1 MHz. Substantial improvements in phasenoise result from the inclusion of the additional filter 250 (e.g.around 10 dB from 3 to 7 MHz, and at least 5 dB from 800 kHz to 10 MHz).

FIG. 11 shows the effect of varying the parameter klp of the additionalfilter 250. Again, the open loop DCO phase noise 270 is shown, alongwith phase noise simulations 271 to 276, respectively corresponding withklp values of 1 to 6. The cutoff frequencies ω_(c) corresponding witheach value of klp are shown in the table below.

klp 1 2 3 4 5 6 ω_(c) (MHz) 4.4 2.2 1.1 0.55 0.28 0.138

As the cut-off frequency ω_(c) gets close to the PLL bandwidth ω_(3 dB)the PLL may become unstable. The optimum settings for this example PLLmay be klp=5, since this provides the largest improvements to phasenoise above 300 kHz, and does not introduce the large peak centered justabove 100 kHz that is associated with klp=6.

This disclosure shows how the out-of-band phase noise of a PLL system(such as an ADPLL) can be improved by reducing the quantization phasenoise contribution from the phase detector in out-of-band frequencyrange by means of an additional low-pass filter before or after the loopfilter. The design effort needed to implement this improvement is quitesmall. The configuration can be chosen such that the overall loopdynamic is hardly changed. There is no problem with stability (which mayoccur in more complex arrangements in which the loop filter is modifiedto try to increase suppression of quantization noise), provided thefilter parameters are selected appropriately. According to thedisclosure, the phase locked loop may be set to higher loop bandwidthswithout degrading the out-of-band phase noise performance. The phaselocked loop described herein works well in a wide range of applications.

The disclose can be applied in the context of a linear, all digitalphase locked loop, as shown in FIG. 7, or in any other controllingscheme that generates quantization noise, for example a PLL in which abang-bang control scheme is used. A bang-bang mode may be a non-linearcontrolling mode in which a quantizer is used to determine a phase error(instead of an adder), and the loop filter may be updated by smallconstant portions accordingly.

From reading the present disclosure, other variations and modificationswill be apparent to the skilled person. Such variations andmodifications may involve equivalent and other features which arealready known in the art of phase locked loops, and which may be usedinstead of, or in addition to, features already described herein.

Although the appended claims are directed to particular combinations offeatures, it should be understood that the scope of the disclosure ofthe present invention also includes any novel feature or any novelcombination of features disclosed herein either explicitly or implicitlyor any generalisation thereof, whether or not it relates to the sameinvention as presently claimed in any claim and whether or not itmitigates any or all of the same technical problems as does the presentinvention.

Features which are described in the context of separate embodiments mayalso be provided in combination in a single embodiment. Conversely,various features which are, for brevity, described in the context of asingle embodiment, may also be provided separately or in any suitablesub-combination. The applicant hereby gives notice that new claims maybe formulated to such features and/or combinations of such featuresduring the prosecution of the present application or of any furtherapplication derived therefrom.

For the sake of completeness it is also stated that the term“comprising” does not exclude other elements or steps, the term “a” or“an” does not exclude a plurality, and reference signs in the claimsshall not be construed as limiting the scope of the claims.

The invention claimed is:
 1. A phase locked loop, comprising: a phasedetector configured to determine a phase difference between a referencesignal and a feedback signal; a digital loop filter configured toperform a filtering operation on a signal derived from the phasedifference and to provide three different control signals; a digitallycontrolled oscillator configured to receive the three different controlsignals and provide an output signal with a frequency that variesaccording to the three different control signals; and a low-pass filteris provided between the phase detector and the digital loop filter andconfigured to reduce quantization noise from the phase detector byhaving a cut-off frequency that is greater than a bandwidth of the phaselocked loop.
 2. The phase locked loop of claim 1, wherein the phaselocked loop has a bandwidth defined by the characteristics of the phasedetector, the digital loop filter and the digitally controlledoscillator.
 3. The phase locked loop of claim 2, wherein the low-passfilter has a cut-off frequency at least 1.2 times the bandwidth of thephase locked loop.
 4. The phase locked loop of claim 2, wherein thelow-pass filter has a cut-off frequency that is at least 100 kHz greaterthan the bandwidth of the phase locked loop.
 5. The phase locked loop ofclaim 1, wherein the low-pass filter comprises a first order InfiniteImpulse Response (IIR) filter.
 6. The phase locked loop of claim 5,wherein the first order IIR filter further comprises: a shift multiplierin a forward path thereof, configured to multiply by an integer power oftwo.
 7. The phase locked loop of claim 1, wherein the digital loopfilter further comprises: an integral path comprising an integrator. 8.The phase locked loop of claim 7, wherein the digital loop filterfurther comprises: a proportional path.
 9. The phase locked loop ofclaim 8, wherein the phase locked loop is configured with a proportionalgain factor k_(p) in the proportional path and an integral gain factork_(i) prior to the integrator in the integral path, wherein: k_(p)≦2⁻¹²;k_(i)≦2⁻¹⁸.
 10. The phase locked loop of claim 1, wherein the digitallycontrolled oscillator further comprises: a switched capacitor LCoscillator.
 11. A receiver comprising the phase locked loop of claim 1.12. The receiver of claim 11, wherein the receiver is a satellite radioreceiver.
 13. The phase locked loop of claim 1, wherein the digital loopfilter is configured to provide a process voltage temperature controlsignal to the digitally controlled oscillator.
 14. The phase locked loopof claim 1, wherein the digital loop filter is configured to provide anacquisition control signal to the digitally controlled oscillator. 15.The phase locked loop of claim 1, wherein the digital loop filter isconfigured to provide a tracking signal to the digitally controlledoscillator.
 16. The phase locked loop of claim 1, wherein the digitalloop filter is configured to provide the three different control signalsto respective switched capacitor banks of the digitally controlledoscillator.
 17. A phase locked loop, comprising: a phase detectorconfigured to determine a phase difference between a reference signaland a feedback signal; a digital loop filter configured to perform afiltering operation on a signal derived from the phase difference and toprovide three different control signals; a digitally controlledoscillator configured to receive the three different control signals andprovide an output signal with a frequency that varies according to thethree different control signals; and a low-pass filter is providedbetween the digital loop filter and the digitally controlled oscillatorand configured to reduce quantization noise from the phase detector byhaving a cut-off frequency that is greater than a bandwidth of the phaselocked loop.